Enhanced virtual renaming scheme and deadlock prevention therefor
US7539850B2 · kind B2 · utility
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13References
21Claims
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Key dates
| Filing date | Jan 27, 2003 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Jan 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.