Self-correcting buffer
US7541852B2 · kind B2 · utility
6Cited by
9References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2006 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Feb 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to convert duty cycle error in an outgoing signal to a DC offset and to provide the DC offset to the capacitor. The DC offset is used to bias the capacitor. The biasing of the capacitor can adjust the DC blocked incoming signal so as to reduce the duty cycle error in the outgoing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.