Logic cell protected against random events
US7542333B2 · kind B2 · utility
0Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2007 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Dec 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.