Semiconductor memory
US7542359B2 · kind B2 · utility
4Cited by
14References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Nov 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing the plurality of remedying bit registers in each memory bank is arranged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.