Frequency offset correction circuit device
US7542527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2005 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Apr 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D3/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit device is provided which can attain more stable operations against noise in a data communication system without increasing the power consumption of an overall system, thereby improving the reliability of data communication. For a demodulation baseband signal (S11) obtained by performing digital processing on an output signal (S6) from an AD converter (6), the maximum value (S12) and the minimum value (S13) are detected as digital values by a maximum value holding circuit (11) and a minimum value holding circuit (12), an averaging circuit (13) obtains an average value (intermediate value) of the maximum value and the minimum value and detects a frequency offset amount (S14), and the frequency offset amount is fed back to a threshold value of data decision (14), so that binarized demodulation data (S15) is outputted in which the offset of the demodulation baseband signal is corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.