Up converter mixer linearization improvement
US7542739B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 2004 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Oct 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0084
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An up conversion mixer has a Gilbert cell arrangement including an input amplification part for producing an amplified signal coupled to a multiplication part, the multiplication part being arranged to multiply the amplified signal by a local oscillator signal and output a mixed signal, the mixer also having a capacitor coupled from a node between the input amplification part and the multiplication part, to a power supply line, for suppressing unwanted high frequency signal components of the output signal of the multiplication part. The linearity of such mixers can be improved considerably by this impedance on the source node of the switch transistors. This capacitance can be placed to either VSS or to VDD. Notably this improvement can be achieved with low power consumption since no additional power is needed for the increased performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.