Patent · US Expired

Hybrid cryptographic accelerator and method of operation thereof

US7543158B2 · kind B2 · utility

23Cited by
9References
20Claims
0Family size

Assignee

Inventor

Key dates

Filing dateMar 23, 2004
Grant dateJun 2, 2009
Priority date—
Expiry dateMar 26, 2026

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F21/72
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

For use in a system-on-a-chip (SoC) having a secure execution environment (SEE) containing secure memory, a cryptographic accelerator, a method of performing cryptography therewith and an SoC incorporating the cryptographic accelerator or the method. In one embodiment, the cryptographic accelerator includes: (1) a key register located within the SEE and coupled to the secure memory to receive a cryptographic key therefrom and (2) data input and output registers located outside of the SEE and coupled to the key register to allow the cryptographic key to be applied to input data arriving via the data input register to yield output data via the data output register.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.