Method and apparatus for reducing false error detection in a redundant multi-threaded system
US7543221B2 · kind B2 · utility
7Cited by
27References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 22, 2004 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Jan 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.