Analog layout module generator and method
US7543262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2005 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Nov 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.