Method for manufacturing a non-volatile electrically alterable memory cell that stores multiple data
US7544566B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2007 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | May 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
Abstract
A self-aligned method for manufacturing an electrically alterable memory device on a semiconductor layer includes (a) forming an insulating layer on the semiconductor layer, (b) depositing a first conductive layer on the insulating layer, (c) forming trench isolation regions along and into the semiconductor layer, (d) depositing a sacrificial material on the first conductive layer, (e) etching the sacrificial material to form isolation channels, (f) forming two gate masks along lateral sides of the sacrificial material, (g) etching the first conductive layer to extend the channels to the insulating layer, (h) etching the sacrificial material to form a control channel, (i) etching the block of the first conductive layer, and (j) filling the control channel with a second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.