Trench gate FET with self-aligned features
US7544571B2 · kind B2 · utility
18Cited by
12References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2006 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Dec 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. A gate electrode recessed in each trench is formed. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.