Method for dividing a high-frequency signal
US7545191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2008 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Apr 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/52
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle time, an off-time of one cycle of the second clock signal being one first clock cycle time less than an on-time of one cycle of the second clock signal; shifting in time the second clock signal by half of a first clock cycle time to generate a third clock signal, the second clock cycle time equal to the third clock cycle time; performing a logical AND of the second clock signal and the third clock signal to generate a fourth clock signal, the third clock cycle time equal to the fourth clock cycle time, an on-time of one cycle of the fourth clock signal equal to an off-time of one cycle of the fourth clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.