Measuring circuit for qualifying a memory located on a semiconductor device
US7545691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2007 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Dec 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A measuring circuit is provided for a memory integrated within a semiconductor device. The measuring circuit includes initializing means and an oscillating loop. The initializing means loadings two complementary values into at least two locations of the memory. The two locations are addressed by a first address and a second address. The oscillating loop comprises a logic circuit for alternatively generating the first address and the second address from data read from the memory so as to successively read data from the first and second memory locations to produce an oscillating signal that has a frequency that depends on internal parameters of the memory. Also provided is a method for qualifying a memory by initializing the memory by loading two complementary values into two locations, and generating an oscillating signal with a frequency that is dependent on internal parameters of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.