Patent · US Active

Decimal floating-point adder

US7546328B2 · kind B2 · utility

29Cited by

22References

44Claims

0Family size

Assignee

Wisconsin Alumni Research Foundation · US

Inventors

Michael Schulte · Madison, US
John Thompson · Markham, CA
Nandini Karra · Folsom, US

Key dates

Filing date	Sep 15, 2004
Grant date	Jun 9, 2009
Priority date	—
Expiry date	Feb 9, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/485
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A decimal floating-point adder is described that performs addition and subtraction on decimal floating-point operands. The decimal floating-point adder includes an alignment unit that receives a first floating-point number and a second floating-point number, and aligns significands associated with the floating-point numbers such that exponents associated with the floating-point numbers have equal values. The decimal-floating-point adder further includes a binary adder that adds the aligned significands. The floating-point adder includes a correction unit and an output conversion unit to produce a final resultant decimal floating-point number. The decimal floating-point adder may be pipelined so that complete resultant decimal floating-point numbers may be output each clock cycle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.