Data packet buffering system with automatic threshold optimization
US7546400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2005 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Feb 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data packet buffering system comprising a data buffer for buffering data packets, a first counter (24) preloaded with the data packet size (32) and decremented at each read clock signal of a number of logical units corresponding to the width of the output bus (18), a second counter (28) preloaded with the data packet size and decremented at each write clock signal of a number of logical units corresponding to the width of the input bus (14), the decrementation of the second counter being started at the same time as the decrementation of the first counter by a start counter signal (38), and a threshold unit (52) for determining the minimum threshold from the contents of the second counter when the first counter has reached zero and providing the minimum threshold to a buffer management logic unit a buffer management logic unit (22) providing write grant signals when data may be read from the data buffer and sent to an output device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.