Information processor having delayed branch function with storing delay slot information together with branch history information
US7546445B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2003 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | May 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In correspondence with an address of a branch instruction, a branch target address Apb, a valid bit V as branch history information, and delay slot information POS on the last position of delay slot instructions are stored in a branch target buffer 241. A branch prediction circuit 23 outputs hit information H/M as to whether or not an input address Ao is coincident with the branch instruction address, the valid bit which is also a branch prediction bit, the information POS, and the branch target address Apb. When a prediction error signal ERR is inactive, the address selection circuit 22 selectively outputs the output of an incrementer 21 and the branch target address Apb, based on the hit information H/M, the delay slot information POS, and the valid bit V.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.