DRAM stacked package, DIMM, and semiconductor manufacturing method
US7546506B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 20, 2006 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Aug 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.