Compact high-speed single-bit error-correction circuit
US7546510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2004 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compact high-speed data encoder/decoder for single-bit forward error-correction, and methods for same. This is especially useful in situations where hardware and software complexity is restricted, such as in a monolithic flash memory controller during initial startup and software loading, where robust hardware and software error correction is not feasible, and where rapid decoding is important. The present invention arranges the data to be protected into a rectangular array and determines the location of a single bit error in terms of row and column positions. So doing greatly reduces the size of lookup tables for converting error syndromes to error locations, and allows fast error correction by a simple circuit with minimal hardware allocation. Use of square arrays reduces the hardware requirements even further.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.