Communications bus for a parallel processing system
US7546570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Jan 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17337
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting data signals into the communications bus. The communications bus includes a plurality of parallel channels, and at least one channel crossover point associated with each cell. Each crossover point implements a regular change in a channel order of the communications bus, such that each access point is coupled to a channel of the communications bus. Propagation delays are reduced by inserting buffers at regular intervals along the length of each channel. An output buffer at a downstream boundary of each power domain of the system prevents undesired currents due to voltage mismatch. The propagation direction of data signals away from the access point, and propagation of data to an adjacent downstream cell can be controlled to reduce bus traffic and power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.