Thin film transistor array panel
US7547588B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2004 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/40
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor (“TFT”) array panel is provided, which includes: first and second gate lines transmitting gate signals to adjacent pixel rows and disposed adjacent to each other; a data line insulated from the first and the second gate lines and the data line; a first thin film transistor connected to the first gate line and the data line and including a first drain electrode overlapping the second gate line; a second TFT connected to the second gate line and the data line, disposed opposite the first TFT with respect to the data line, and including a second drain electrode overlapping the first gate line; a first pixel electrode connected to the first drain electrode and overlapping the second gate line; and a second pixel electrode connected to the second electrode and overlapping the first gate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.