Semiconductor device and method of manufacturing the same
US7547950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2007 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Nov 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A conventional semiconductor device has a problem that it is difficult to obtain a desired breakdown voltage characteristic due to a reduction in a punch-through breakdown voltage between drain and source regions. In a semiconductor device according to the present invention, a P type diffusion layer is formed in an N type epitaxial layer. An N type diffusion layer as a back gate region is formed in the P type diffusion layer. The N type diffusion layer is formed by self-alignment using a drain electrode. This structure makes it possible to increase an impurity concentration of the N type diffusion layer in a vicinity of a P type diffusion layer as a source region. As a result, it is possible to improve a punch-through breakdown voltage between the drain and the source regions, and to achieve a desired breakdown voltage characteristic of the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.