Patent · US Active

Delay line with delay cells having improved gain and in built duty cycle control and method thereof

US7548104B2 · kind B2 · utility

3Cited by

14References

15Claims

0Family size

Assignee

Cosmic Circuits Private Limited · IN

Inventors

Prasenjit Bhowmik · Bengaluru, IN
Sundararajan Krishnan · Bengaluru, IN
G. Sriram · Bengaluru, IN

Key dates

Filing date	Jun 10, 2007
Grant date	Jun 16, 2009
Priority date	—
Expiry date	Jun 10, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00045
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.