Memory array with readout isolation
US7548453B2 · kind B2 · utility
7Cited by
20References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.