Memory array with readout isolation
US7548454B2 · kind B2 · utility
6Cited by
24References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Aug 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate the elements in the array from the external load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.