Method and apparatus for dynamic power adjustment in a memory subsystem
US7548481B1 · kind B1 · utility
6Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2006 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Dec 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An aspect of the invention relates to a method of dynamically adjusting power consumption of a random access memory (RAM) coupled to a processor. Frequency of a memory clock signal coupled to the RAM is reduced. At least one supply voltage coupled to the RAM is reduced. At least one latency parameter of the RAM is configured in response to the reduced frequency and the reduced at least one supply voltage. The RAM may then be re-initialized. In this manner, voltage supplied to the RAM is reduced, thereby reducing power consumption in the RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.