Enhanced output impedance compensation
US7551020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2007 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | May 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0264
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.