Phase adjustment in phase-locked loops using multiple oscillator signals
US7551039B2 · kind B2 · utility
1Cited by
3References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Jan 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/143
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase-locked loop (PLL) logic comprises an oscillator that produces a first oscillator signal and phase detect logic that determines a phase difference between the first oscillator signal and a second oscillator signal. After the second oscillator signal is replaced by a third oscillator signal, the phase detect logic determines another phase difference between the first oscillator signal and the third oscillator signal. The PLL removes the phase difference from the another phase difference to produce an intermediate signal. The oscillator adjusts the first oscillator signal using the intermediate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.