Iterative memory cell charging based on reference cell value
US7551486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Jun 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods, including computer software for writing to a memory device include applying charge to each of multiple memory cells for storage of a selected data value in each memory cell. The memory cells include a first reference memory cell, and each data value is selected from a group of possible data values. Each possible data value has a corresponding target voltage level, and the first reference memory cell has a corresponding predetermined first reference target voltage level. The voltage level in the first reference memory cell is detected. A determination is made whether the voltage level in the first reference memory cell is less than the first reference target voltage level. Additional charge is applied to the memory cells upon the determination that the voltage level in the first reference memory cell is less than the first reference target voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.