Semiconductor memory utilizing a method of coding data
US7551514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2007 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Dec 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device utilizing a data coding method in an initial operation. The device includes a plurality of counters that count the number of data bits and flag information data bits. A data coding unit selectively applies a first and second operation mode. The first operation mode codes the data of the first through nth data groups such that the counted number of data bits in a first logic state is minimized. The second operation mode codes the data of the first through nth data groups such that the difference between the number of data bits and flag information bits in the first and second logic state are minimized. This prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.