Selectively inclusive cache architecture
US7552288B2 · kind B2 · utility
13Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2006 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Jul 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.