Methods and systems for grouping instructions using memory barrier instructions
US7552317B2 · kind B2 · utility
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1References
34Claims
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Assignee
Inventor
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Feb 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and articles of manufacture consistent with the present invention provide a memory instruction manager for managing the execution of instructions associated with a program. The memory instruction manager assigns a first group identifier to a first instruction associated with a program and to a second instruction associated with the program, and provides, after the first instruction, a memory barrier instruction having the first group identifier such that one or more processors with access to the program are inhibited from executing the second memory instruction until the first memory instruction is executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.