High speed level shifter circuit in advanced CMOS technology
US7554360B1 · kind B1 · utility
4Cited by
4References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 4, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Apr 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018514
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit for shifting from a first voltage level technology (such as 0.9 volt) to a second level voltage technology (such as 3.3 volt) with increased switching speed. The increased speed is achieved by adding a boost circuit to the pull-up transistors to boost the switching speed and shut itself down after the transition. The level shifter circuit does not require intermediate level transistors or intermediate level voltage sources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.