Circuit and method for adjusting impedance
US7554417B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2008 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Mar 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An impedance adjusting circuit includes a semiconductor device accommodated in a semiconductor device case which has case pins and having a folded conductive line; an external reference resistor connected between a positive power supply line and a first one of the case pins, wherein a first line between the first case pin and the semiconductor device has a specific resistance; a first reference voltage generation resistor connected between the power supply line and a second one of the case pins; a second reference voltage generation resistor connected between the ground and a third one of the case pins; a resistance circuit comprising a second line between the second case pin and the folded conductive line and a third line between the third case pin and the folded conductive line, wherein a resistance between the second case pin and the third case pin is equal to the specific resistance; and a fourth line connected from the semiconductor device to the ground through the second reference voltage generation resistor and having a resistance equal to the specific resistance. The semiconductor device includes an adjusting circuit having a buffer and configured to adjust an output impeda…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.