System and method for automatically adjusting the clock phase of a display in real-time
US7554519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2004 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jan 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/02
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a system and method for adjusting clock phase in a digital display. The display 10 may include a target analog-to-digital converter 104 that generates a first digital signal based on an analog input signal and a first clock signal (CLK1). The system 100 includes a first clock phase adjustment circuit 108, which provides CLK1 to the target analog-to-digital converter 104. A second analog-to-digital converter 106 receives at least a portion of the analog input signal and a second adjusted clock signal (CLK2), and generates a second digital signal based on these inputs. A second clock phase adjustment circuit 100 is communicatively coupled to the second analog-to-digital converter 106, and transmits CLK2 to the second analog-to-digital converter. A controller 112 receives the second digital signal from the second analog-to-digital converter 106 and uses the signal to determine a preferred phase of CLK2. The controller 112 then causes the first clock phase adjustment circuit to adjust the phase of CLK1 based on the preferred phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.