Booster circuit, semiconductor device, and display device
US7554537B2 · kind B2 · utility
4Cited by
1References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2004 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | May 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/009
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A booster circuit including first to Mth power supply lines (M is an integer larger than 3) and first and second charge-pump circuits. Each of the charge-pump circuit has first to (M−2)th boost capacitors, wherein the jth boost capacitor (1≦j≦M−2, j is an integer) is connected between the jth power supply line and the (j+1)th power supply line in a first period and is connected between the (j+1)th power supply line and the (j+2)th power supply line in a second period subsequent to the first period. Each of the charge-pump circuits generates a boosted voltage by a charge-pump operation in different phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.