Flash memory device employing disturbance monitoring scheme
US7554847B2 · kind B2 · utility
54Cited by
5References
38Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Aug 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device comprises a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising a disturbed string coupled to a disturbed bit line. In a program operation of the flash memory device, a voltage level of the disturbed bit line is detected to detect program or pass voltage disturbance in the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.