Delay locked loop circuit, digital predistortion type transmitter using same, and wireless base station
US7555058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2005 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Feb 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/331
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed are a delay locked loop circuit capable of accurately extracting nonlinear distortion superimposed on an output of a digital predistortion type transmitter, the digital predistortion type transmitter, and a wireless base station using the same. The delay locked loop circuit outputting a smoothed signal to the variable delay element, in which delay control is implemented for checking distortion occurring to the output IQ signals due to the same passing through the analog circuit by means of the variable delay element. Either the first input IQ signals or the second input IQ signals are signals generated as a result of output IQ signals Io, Qo undergoing digital-to-analog conversion, and again undergoing analog-to-digital conversion after passing through an analog circuit. In particular, an IIR filter may be used for the variable delay element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.