Asymmetric data path media access controller
US7555574B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Feb 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/05
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.