Fast buffer pointer across clock domains
US7555590B2 · kind B2 · utility
7Cited by
23References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Mar 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of a second clock signal, said first and second clock signals having a known repeat relationship, the retiming circuitry comprising a plurality of delay elements for delaying said data signal; a plurality of inputs connected to said delay elements for receiving said data signal at respectfully different delays; selection means for selecting the data signal at one of said inputs based on said known repeat relationship; and an output for outputting said selected data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.