Simultaneous multi-threading in a content addressable memory
US7555593B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jun 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/7453
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A CAM device having two execution pipelines includes control logic and a CAM core. The CAM core includes a plurality of independently searchable CAM arrays for storing CAM words. The control logic receives a first request that selects any number of the CAM arrays for a first compare operation, and receives a second request that selects any number of the CAM arrays for a second, separate compare operation. The control logic determines whether the same CAM array is selected by both requests. If not, the control logic schedules the first and second compare operations to be executed simultaneously in the CAM core. Otherwise, the control logic schedules the first and second compare operations for sequential executionuses a suitable arbitration technique to determine the order in which the first and second compare operations will be executed in the CAM core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.