DRAM interface circuits that support fast deskew calibration and methods of operating same
US7555668B2 · kind B2 · utility
3Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jan 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.