Method and apparatus for monitoring bit-error rate
US7555685B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 21, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jan 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A test set for evaluating network performance is described, and which may include an output device, a processor, a power supply, a memory unit, and a control terminal. The test set may be configured to receive a user-entered selection of one of a plurality of different bit-error rate profiles and generate a test signal exhibiting the selected bit-error rate profile. The test set may also supply the test signal exhibiting the selected bit-error rate profile to a network under test. In addition, the test set may receive as an input, an output from the network under test. The output may include the test signal exhibiting the selected bit-error rate. The test set may evaluate the received test signal and determine the performance of the network in response to the received test signal exhibiting the bit-error rate. The test set may then output the results of the evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.