Pre-emphasis circuit including slew rate controllable buffer
US7557602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Oct 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K6/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.