Topology for a n-way XOR/XNOR circuit

US7557614B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Stefan Bonsels · Stuttgart, DE
• Martin Padeffke · Hildrizhausen, DE
• Tobias Werner · Holzgerlingen, DE
• Alexander Woerner · Eppelheim, DE

Key dates

• Filing date: Jul 15, 2008
• Grant date: Jul 7, 2009
• Expiry date: Jul 15, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/215
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A method for configuring a n-way XOR/XNOR circuit comprises providing a plurality of top stacks of PFETs each including at least three PFETs electrically connected between a high logic level and an output logic connection, providing a plurality of bottom stacks of NFETs each including at least three NFETs electrically connected between a low logic level and the output logic connection, connecting a source or a drain of the outermost PFET in each top stack to a source or a drain of a corresponding NFET in each bottom stack to generate inverted logic signals, inputting at least three input logic states to the stacks of PFETs to selectively connect or disconnect the output logic connection to the high logic level, inputting at least three input logic states to the stacks of NFETs to selectively connect or disconnect the output logic connection to the low logic level, and outputting a logic signal from the output logic connection.