Limited switch dynamic logic cell based register
US7557616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2008 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Jul 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.