Direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization
US7557661B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2006 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | May 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level. A DDS circuit provides a clock output and has an input for receiving a rational number. The rational number represents a ratio between the frequency of the clock output and the frequency of another stable clock provided to the circuit. In one implementation, a phase output of the DDS circuit is compared to a phase determined from an incoming timing reference and in another implementation, the low-jitter clock output is utilized to generate a phase number via a counter that is clocked by the clock output and captured by the timing reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.