Digital PLL for a system-on-chip for digital control of electronic power devices
US7557663B2 · kind B2 · utility
1Cited by
15References
17Claims
0Family size
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Key dates
| Filing date | Jun 17, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Jun 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1225
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase locked loop (DPLL) comprising a digitally implemented voltage controlled oscillator (VCO) for producing a VCO feedback signal, a phase error counter which includes a digital phase-frequency detector for producing a first phase error signal, a quadrature phase detector for producing a second phase error signal and an adder for adding the first and second phase error signals to obtain a combined phase error signal, and two programmable dividers used to cooperatively determine the VCO feedback signal and to provide a DPLL output line sync value synchronized with an input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.