Power saving in memory arrays
US7558104B2 · kind B2 · utility
3Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Aug 21, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.