Nonvolatile semiconductor memory device
US7558117B2 · kind B2 · utility
11Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Jan 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a nonvolatile semiconductor memory device which can read and verify a cell with a negative threshold voltage by biasing voltages of a source line and well line to a positive voltage. The nonvolatile semiconductor memory device includes a voltage control circuit which applies a select gate voltage obtained by adding the biased positive voltage to a voltage set at read time of a cell with a positive threshold voltage to a select gate at a read time and verify time for the cell with the negative threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.