Memory interface to bridge memory buses
US7558124B2 · kind B2 · utility
15Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2006 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Dec 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.